Next revision
|
Previous revision
Next revision
Both sides next revision
|
publications [2017/06/05 15:24] arijit created |
publications [2017/06/18 09:13] arijit [Journals] |
=====Publications===== | ======Publications====== |
To be updated soon. | =====Journals===== |
| * Nilotpal Chakraborty, Arijit Mondal and Samrat Mondal, "//Intelligent Scheduling of Thermostatic Devices for Efficient Energy Management in Smart Grid//", IEEE Transactions on Industrial Informatics, 2017 (Accepted). |
| * Arijit Mondal, P. P. Chakrabarti, Pallab Dasgupta, “//Symbolic Event Propagation Based Minimal Test Set Generation for Robust Path Delay Faults//”, ACM Transactions on Design Automation of Electronic Systems, Volume 17 Issue 4, October 2012. |
| * Arijit Mondal, P. P. Chakrabarti, Pallab Dasgupta, “//Statistical static timing analysis using symbolic event propagation”, IET Circuit, Device and Systems//, Vol 1, No 4, pages 283-291, 2007. |
| * Arijit Mondal, P. P. Chakrabarti, “//Reasoning about timing behavior of digital using symbolic event propagation and temporal logic//”, IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems, Vol 25, No. 9, pages 1973-1814, 2006. |
| |
| =====Conferences===== |
| * Arnab Sarkar, Arijit Mondal, "//Partitioned Fair Round Robin: A Fast andAccurate QoS Aware Scheduler for Embedded Systems//", VLSI Design Conference (VLSID) 2016. |
| * Jaishree Mayank, Arijit Mondal, "//Performance optimization of real timecontrol systems using variable time period//". VLSI Design and Test Symposium (VDAT) 2015. |
| * Arijit Mondal, P. P. Chakrabarti and Pallab Dasgupta, “//Accelerating Synchronous Sequential Circuits using an Adaptive Clock//”, Proceedings of VLSI Design Conference 2010. |
| * Arijit Mondal, P. P. Chakrabarti, Pallab Dasgupta, “//Timing analysis of sequential circuits using symbolic event propagation//”, International Conference on Computing: Theory and Applications, 2007. |
| * Diganchal Chakraborty, P. P. Chakrabarti, Arijit Mondal, Pallab Dasgupta, “//A framework for estimating peak power in gate level circuits//”, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 573-582, 2006 (LNCS). |
| * Arijit Mondal, P. P. Chakrabarti and C. R. Mandal, “//A New Approach to Timing Analysis using Event Propagation and Temporal Logic//”, Design Automation and Test in Europe (DATE), Paris 2004. |
| |
| |